1. Field of the Invention
The present invention is related to a double-gate liquid crystal display device and related driving method, and more particularly, to a double-gate liquid crystal display device and related driving method which improve display quality.
2. Description of the Prior Art
Liquid crystal display (LCD) devices with thin appearance have gradually replace traditional bulky cathode ray tube (CRT) displays and been widely used in various electronic products, such as notebook computers, personal digital assistants (PDAs), flat panel TVs, or mobile phones. In a typical LCD device, a timing controller is used for generating various control signals, based on which a source driver and a gate driver scan the pixels on the panel for displaying images. The LCD device is driven according to pixel arrangement. For the same resolution, an LCD panel having double-gate pixel arrangement requires twice the number of gate lines (more gate driving chips) and half the number of data lines (fewer source driving chips) when compared to an LCD panel having single-gate pixel arrangement. Since gate driving chips are less expensive and consume less power, double-gate pixel arrangement may reduce manufacturing costs and power consumption.
FIG. 1 is a diagram illustrating a prior art LCD device 100 having double-gate pixel arrangement. The LCD device 100 includes an LCD panel 110, a source driver 120, a gate driver 130, and a timing controller 140. A plurality of data lines DL1-DLm, a plurality of gate lines GL1-GLn, and a pixel matrix are disposed on the LCD panel 110. The pixel matrix includes a plurality of pixel units PL and PR each having a thin film transistor (TFT) switch, a liquid crystal capacitor CLC and a storage capacitor CST, and respectively coupled to a corresponding data line, a corresponding gate line and a common voltage VCOM. In the LCD device 100, two adjacent columns of pixel units PL and PR are coupled to the same data line, wherein the odd-numbered columns of pixel units PL are coupled to the odd-numbered gate lines GL1, GL3, . . . , GLn-1 and the even-numbered columns of pixel units PR are coupled to the even-numbered gate lines GL2, GL4, . . . , GLn.
The timing controller 140 is configured to generate control signals for operating the source driver 120 and the gate driver 130, such as a latch pulse signal TP and an image signal DATA. According to the latch pulse signal TP, the gate driver 130 sequentially outputs the gate driving signals SG1-SGn to the corresponding gate lines GL1-GLn. According to the image signal DATA, the source driver 120 outputs the data driving signals SD1-SDm associated with display images to the corresponding data lines DL1-DLm, thereby charging the liquid crystal capacitors CLC and the storage capacitors CST of the corresponding columns of pixel units.
FIG. 2 is a timing diagram illustrating the operation of the prior LCD device 100. FIG. 2 shows the latch pulse TP, the gate driving signals SG1-SG4, and the pixel voltages V+−, V−−, V−+, V++. The latch pulse TP is a pulse signal with a constant trigger frequency so that each pixel unit has a constant charge time TON during each period. The pixel voltages V+−, V−−, V−+, V++ correspond to the voltage levels of two adjacent pixel units PL and PR in a certain row of pixel units which are coupled to the same data line. Assuming that the polarities of the data driving signals during the periods T1-T5 are respectively positive, negative, negative, positive and positive (as indicated by “+” and “−” in FIG. 2), the two rows of pixel units coupled to the gate lines GL1-GL4 are used for illustration. During the period T1, the gate driving signal SG1 is at enable level (high level), and the positive data driving signal precharges the odd-numbered columns of pixel units PL in the first row of pixel units via the turned-on TFT switch; during the period T2, the gate driving signals SG1 and SG2 are both at enable level, and the negative data driving signal main-charges the odd-numbered columns of pixel units PL and precharges the even-numbered columns of pixel units PR in the first row of pixel units via the turned-on TFT switch; during the period T3, the gate driving signals SG2 and SG3 are both at enable level, and the negative data driving signal main-charges the even-numbered columns of pixel units PR in the first row of pixel units and precharges the odd-numbered columns of pixel units PL in the second row of pixel units via the turned-on TFT switch; during the period T4, the gate driving signals SG3 and SG4 are both at enable level, and the positive data driving signal main-charges the odd-numbered columns of pixel units PL and precharges the even-numbered columns of pixel units PR in the second row of pixel units via the turned-on TFT switch; during the period T5, the gate driving signal SG4 is at enable level, and the positive data driving signal charges the even-numbered columns of pixel units PR in the second row of pixel units via the turned-on TFT switch.
In other words, the odd-numbered columns of pixel units PL in the first row of pixel units, whose voltage level may be represented by V+−, receive positive data driving signals during the corresponding precharge period T1 and receive negative data driving signals during the corresponding main-charge period T2; the even-numbered columns of pixel units PR in the first row of pixel units, whose voltage level may be represented by V−−, receive negative data driving signals both during the corresponding precharge period T2 and the corresponding main-charge period T3; the odd-numbered columns of pixel units PL in the second row of pixel units, whose voltage level may be represented by V−+, receive negative data driving signals during the corresponding precharge period T3 and receive positive data driving signals during the corresponding main-charge period T4; the even-numbered columns of pixel units PR in the second row of pixel units, whose voltage level may be represented by V++, receive positive data driving signals during the corresponding precharge period T4 and the corresponding main-charge period T5.
If a pixel unit receives data driving signals having the same polarity during its main-charge and precharge periods, the pixel unit has sufficient time to reach its predetermined level (as illustrated by V++ or V−−). In this case, the amount of charges written into the pixel unit is represented by the striped region marked by A2 and A4 in FIG. 2. If a pixel unit receives data driving signals having opposite polarities during its main charge and precharge periods, it takes longer for the pixel unit to reach its predetermined level since its voltage level needs to be reversed (as illustrated by V+− or V−+). In this case, the amount of charges written into the pixel unit is represented by the striped region marked by A1 and A3 in FIG. 2. As illustrated in FIG. 2, for displaying images having the same grayscale value, certain pixel units may provide downgraded display quality due to insufficient charge time (the area of A1/A3 is smaller than that of A2/A4).